Samsung and SK Hynix respond to HBM4E heat dissipation, AI intermediary layer may expand to 40 times

TrendForce reported on October 12, citing Chosun Biz, that as AI packaging accommodates more computing and storage chips, the intermediary layer connecting computing chips and HBM is expected to significantly increase in size, making next-generation HBM cooling more important. Samsung Electronics is preparing multiple technologies to address the cooling challenges of HBM4E, which is scheduled to begin mass production next year.

Currently, the area of the AI intermediary layer is about 5.5 times the maximum exposure area of 858 square millimeters of an EUV lithography machine. Semiconductor equipment industry insiders expect that the intermediary layer carrying HBM could expand to 9 times, 12 times that area, and ultimately about 40 times. Reasons include limitations in process miniaturization and the popularity of chiplet-style 2.5D packaging, where multiple computing chiplets and HBM stacks are placed on the same intermediary layer, making it difficult for a single advanced process chip to meet AI computing power demands.

Samsung is considering hybrid copper bonding and thermal path blocks. The former replaces the micro bumps between stacked DRAM chips with direct copper-to-copper connections, which can reduce inter-layer gaps, make the stack thinner, and improve heat dissipation, a technology Samsung showcased at NVIDIA GTC in March 2026. The thermal path block establishes a dedicated thermal path in the D2D PHY area responsible for high-speed transmission between HBM base chips and GPUs, which Samsung is validating with HBM4E and plans to implement in HBM5. According to ETNews, SK Hynix's iHBM places high thermal conductivity but electrically insulating cooling materials around the heat-concentrated D2D PHY, which is expected to reduce thermal resistance by about 30%.