Huawei Ascend 950PR's matrix computing speed is only 43% of H100

The semiconductor research organization SemiAnalysis has released the actual test results of Huawei's Ascend 950PR. The organization selected 1,055 sets of commonly used matrix calculations for large models. Huawei's own underlying program has allowed the 950PR to achieve 86% of its theoretical computing power, higher than NVIDIA's H100 at 75.5%; however, the actual computation speed is still only 43% of the H100, and only 21% compared to the relatively newer B300. This set of results has not yet utilized the newly ported operators from DeepSeek.

DeepSeek is working on reducing data movement and waiting from the software side. In attention computation, after adjusting storage with FlashMLA, the two sets of data that originally needed to be read separately can now be retrieved at once; TileLang allows the chip to compute while preloading the next batch of data. SemiAnalysis measured that automatic scheduling has reduced the time for some small computing tasks by up to about 40%. DeepSeek has also ported DeepEP, which is responsible for MoE expert communication, but communication and computation will still compete for memory bandwidth, and Huawei plans to continue improving the firmware.

Last year, DeepSeek attempted to train R2 using Huawei's Ascend chips, but even with Huawei engineers on-site for assistance, it could not be completed due to issues related to chip stability, inter-card communication, and software support. This year, both parties continue to collaborate, and by the end of September, DeepSeek focused on publicly releasing six sets of Ascend adaptation code. In October, it was reported that Huawei is adjusting the next generation of chip designs according to DeepSeek's model requirements. The 950PR tested this time is mainly aimed at inference input processing, while DeepSeek is preparing to use the 950DT for large-scale pre-training as early as the end of the year. Previously, both parties had conducted tests at the thousand-card level, but to enable tens of thousands of chips to complete a round of large model training continuously, more complex coordination and stability issues still need to be resolved.