DIGITIMES: CPO bottlenecks shift from materials to packaging and integration, panel-level packaging becomes a key entry point for Taiwan

According to DIGITIMES, at the Semicon Network Summit 2026, industry representatives pointed out that the bottleneck in the silicon photonics industry has shifted from materials to packaging precision and heterogeneous integration. Marvell's CTO stated that copper interconnects are nearing their physical limits, and end-to-end optical interconnects are inevitable.

TNO/Holst Centre pointed out that the real challenge for CPO is integrating optical materials such as LiNbO3 and InP with the CMOS platform. TSIA indicated that the packaging stage now requires micron-level fiber alignment precision, and Taiwan has a globally leading advantage in the chip and packaging fields. TNO further noted that panel-level packaging is a key opportunity for Taiwan, leveraging large-size glass substrate processing experience to support the large-scale demand for optical interconnects in data centers, but there are still technical gaps in equipment such as Chip-to-Wafer bonding. Marvell stated that its reliance on the Taiwanese supply chain for silicon photonic chips is increasing.