packaging

On September 7, China's leading packaging and testing company Changdian Technology announced plans to raise no more than 6.5 billion yuan (approximately 968 million USD) through a private placement of shares, aimed at expanding advanced packaging capacity for AI chips and related technology research and development.The funds raised will primarily be directed towards the construction of production lines for high-density system-in-package and wafer-level packaging aimed at AI computing chips, in response to order demands from clients such as NVIDIA and AMD. Changdian Technology stated that the bandwidth and heat dissipation requirements for packaging technology have significantly increased for AI chips, and existing capacity is nearing full operation. This fundraising plan still requires approval from the shareholders' meeting and regulatory authorities.

According to DIGITIMES, at the Semicon Network Summit 2026, industry representatives pointed out that the bottleneck in the silicon photonics industry has shifted from materials to packaging precision and heterogeneous integration. Marvell's CTO stated that copper interconnects are nearing their physical limits, and end-to-end optical interconnects are inevitable.TNO/Holst Centre pointed out that the real challenge for CPO is integrating optical materials such as LiNbO3 and InP with the CMOS platform. TSIA indicated that the packaging stage now requires micron-level fiber alignment precision, and Taiwan has a globally leading advantage in the chip and packaging fields. TNO further noted that panel-level packaging is a key opportunity for Taiwan, leveraging large-size glass substrate processing experience to support the large-scale demand for optical interconnects in data centers, but there are still technical gaps in equipment such as Chip-to-Wafer bonding. Marvell stated that its reliance on the Taiwanese supply chain for silicon photonic chips is increasing.

According to sources in the materials industry, on September 2, TSMC is expected to continue using traditional micro-bump technology rather than hybrid bonding in the short term for connecting high-bandwidth memory (HBM) with AI accelerators in advanced packaging. Considering the development cycle of related materials, finer pitch micro-bumps are expected to be used until the later stages of HBM4 and the early stages of HBM5. TSMC has requested its materials and equipment partners to develop bonding and underfill solutions for approximately 5-micron bumps, with suppliers from South Korea and Japan beginning development, and mass production of 5μm bumps expected to start in the second half of 2028.Currently, the bump height of the third-generation extended HBM, namely HBM3E, is about 15-25μm, while HBM4 is close to about 10μm. Japanese material suppliers have previously stated that it is difficult to guarantee quality below 15μm. The reduction and refinement of bumps are due to the height limitations of HBM cubes and the demand for higher interconnection density. JEDEC specifies that the maximum height for HBM stacks is 775μm. In TSMC's advanced CoWoS packaging, the HBM stacks assembled by GPU and memory suppliers are mounted onto the silicon interposer via micro-bumps, with the 16-layer DRAM chip stacks completed within HBM packaging by SK hynix and Samsung Electronics.The first and second generations of HBM used larger solder bumps, while micro-bumps became mainstream around the HBM3 generation. SK hynix uses the MR-MUF process, while Samsung Electronics uses TC-NCF. Hybrid bonding allows for thinner and denser interconnections through direct bonding of copper pads; TSMC has utilized this on its SoIC platform for logic chip stacking, but HBM still connects to the interposer using micro-bumps.

According to a report by the Economic Daily, ASE Technology Holding benefited from the increased capacity of Google TPU, significantly adding advanced packaging and testing orders. Intel is accelerating the promotion of its EMIB advanced packaging platform while simultaneously expanding its outsourcing orders to ASE Technology Holding, with the previously raised testing quotes showing benefits. Google continues to increase its AI capital expenditures to expand data centers, using TPU to support the Gemini large model, AI agents, and Google Cloud services. The market estimates that Google TPU will enter a large-scale production phase by 2028, with shipments expected to reach 12 to 15 million units. ASE Technology Holding has mastered 2.5D, 3D advanced packaging, and high-end testing technologies, and Google is also expanding its use of TSMC's advanced processes and CoWoS capacity.Intel is racing to advance its EMIB packaging platform, with major cloud companies like Meta and Google successively adopting the EMIB and EMIB-T platforms. ASE Technology Holding, positioned as a pure testing and packaging foundry, can directly procure organic embedded silicon bridge substrates to undertake backend wafer-level assembly and high-end testing services. Wu Tianyu, the Chief Operating Officer of ASE Technology Holding, believes that Intel's EMIB and TSMC's CoWoS are not zero-sum competitors. As the testing time for AI chips lengthens, the costs of equipment, materials, and labor are rising, and high-end packaging and testing capacity is becoming increasingly tight. Major testing and packaging factories have gradually raised prices based on products, capacity, and customer conditions, with increases of about 5% to 10%.

SK Hynix CEO Kwak Noh-Jung stated that the company is exploring ways to deepen cooperation with Japanese memory chip customers and suppliers, and is cautiously assessing how to jointly develop the NAND flash memory market. Regarding the company's significant indirect stake in Kioxia, he mentioned that there are currently "no definite plans."After Toshiba's recent divestment, SK Hynix's investment vehicle BCPE Pangea Cayman2 has become Kioxia's largest shareholder, holding a 14.19% stake. SK Hynix holds bonds that can be converted into nearly all voting rights of this investment vehicle; according to a previous agreement, its voting rights cannot exceed 15% before 2028 without Kioxia's consent.In addition, SK Hynix is investing over $4 billion to build its first U.S. HBM packaging facility in Indiana. The cleanroom of the factory is expected to be operational by October 2028, with mass production of the next generation HBM planned for the second half of 2029, and it is expected to employ about 1,000 people once fully operational. The company is also still evaluating the possibility of listing its U.S. NAND subsidiary Solidigm, but no decision has been made yet.

Apple's first 2-nanometer M6 chip officially debuts, equipped with a 12-core CPU, 12-core GPU, and dual 16-core neural network engines, with unified memory bandwidth reaching up to 170GB per second, initially featured in the new Mac mini. This chip is manufactured by TSMC using a 2-nanometer process and is the first to adopt gate-all-around (GAA) nanosheet transistors, making it the world's first consumer-grade 2-nanometer chip.The supply chain is focused on the subsequent high-end M series packaging architecture. Based on the Fusion Architecture of the previous generation M5 Pro, M5 Max, and the four-die design of M5 Ultra, Apple chips have transitioned from a single large die to a modular design. Future M6 Pro, Max, or Ultra are expected to enhance advanced packaging requirements such as SoIC-MH and WMCM, increasing interconnect density with SoIC-MH and integrating logic, LPDDR memory, and high-speed I/O with WMCM.TSMC is actively preparing for expansion, with Zhunan AP6 as the main mass production base for SoIC, Longtan AP3 upgrading to WMCM, and Chiayi AP7 taking on related capacity. Analysts estimate that WMCM's monthly production capacity will reach about 60,000 units by the end of 2026 and over 120,000 units in 2027. Equipment manufacturers such as Hongshuo, Junhua, Yinneng, and material manufacturers Changxing, Xinying Materials, and Yongguang are expected to benefit.

On August 24, SK Hynix is introducing advanced packaging technologies, including Intel's EMIB, for its next-generation HBM solutions and plans to eventually enter the 3D packaging era. At the 2026 Hot Chips conference, SK Hynix's Vice President of Packaging Engineering, Jaesik Lee, delivered a presentation titled "Advanced Packaging for High Bandwidth Memory," explaining how the company will leverage advanced packaging technologies to accelerate its HBM product roadmap.Currently, SK Hynix is exploring methods such as hybrid bonding to break through the limitations of 16-layer stacking. In the future, SK Hynix also plans to address power consumption challenges by increasing the number of TSVs, improving IO speeds of logic process integration, and optimizing power distribution networks. As of the time of publication, SK Hynix's stock rose by 1.71%.

According to the Economic Daily, TSMC's advanced packaging CoWoS capacity is in short supply, and it has been reported that some backend orders have overflowed to Intel's factory in Malaysia, where Intel is assisting with packaging using part of its capacity to serve common major customers, breaking the past ecosystem competition norms. TSMC Chairman Wei Zhejia previously stated at a conference call that TSMC focuses on advanced packaging in the frontend and welcomes "more manufacturers to supply capacity" for the shortage in the backend, providing flexible alternatives for common customers.The report points out that the bottleneck in advanced packaging capacity mainly lies in the backend ramp-up speed being lower than that of the frontend process, and the widening gap in CoWoS capacity has forced orders to overflow. SemiAnalysis Chipbook data shows that approximately $1.3 billion worth of HBM has been shipped to Malaysia, and industry analysis indicates that Intel's local factory should already have the capability for large-scale HBM integration. Intel CEO Pat Gelsinger stated that the EMIB-T technology is ensuring reliable yield, and in the context of insufficient CoWoS capacity, "Intel is in a unique position to provide support." Companies with overlapping supply chains such as Unimicron, ASE Technology Holding, and Jiadeng are expected to benefit simultaneously, with Unimicron's stock price rising over 7% on that day. Intel's EMIB-T related applications are targeted for mass production by 2027.

According to Taiwanese media reports, Intel's next-generation advanced packaging technology EMIB-T is facing severe yield challenges. ABF substrate supplier Unimicron stated during its earnings call on July 29 that the technology is "not yet mature," and the yield target for three EMIB-T substrate suppliers (Unimicron, Ibiden, and Shinkawa) during the initial mass production phase at the end of 2027 is only 50%.EMIB-T is Intel's advanced packaging solution that competes with TSMC's CoWoS-L, differing in that it embeds the silicon bridge directly into the substrate rather than using a silicon interposer, making substrate suppliers a key factor in determining success or failure. Google's ninth-generation TPU has confirmed that it will adopt EMIB-T packaging when it goes into mass production in 2028, with MediaTek responsible for chip co-design. If the chip successfully goes into mass production, its shipment volume is expected to challenge NVIDIA. Unimicron stated that the customer (Intel) has provided a profit guarantee mechanism, ensuring that suppliers can remain profitable even if yields are poor, and that profit margins will exceed the company's average level after achieving the 50% yield target. Currently, there is still considerable uncertainty about whether EMIB-T can achieve its mass production target by the end of 2027.

According to the Electronic Times, TSMC plans to further expand the outsourcing scale of the CoW (Chip-on-Wafer) segment in its CoWoS advanced packaging, entrusting more packaging orders to ASE and other OSAT manufacturers. CoWoS is TSMC's 2.5D packaging technology that connects AI processors such as GPUs with HBM through an intermediary layer, where CoW is the step of combining the chip with the intermediary layer, and WoS is the step of packaging the substrate. Previously, TSMC mainly outsourced the WoS segment, with only a small portion of CoW being entrusted.This move aims to alleviate the packaging capacity bottleneck caused by the continuous surge in demand for AI chips. TSMC holds about 90% of the global AI chip manufacturing market, but as the demand for self-developed chips from manufacturers like Nvidia and AI data centers skyrockets, capacity has become difficult to meet. Industry insiders expect OSATs to significantly increase equipment investment, especially in post-process areas such as wafer cutting and bonding. Several laser processing and bonding equipment suppliers in South Korea have been confirmed to be negotiating with OSATs regarding the supply of CoW equipment.

According to SolanaFloor, Solana's "Resource and Inclusion Fee" proposal SGP-0003 has entered the support stage. If it receives 15% active staking support, the proposal will proceed to a full governance vote.If implemented, the daily SOL burn amount is expected to increase from the current 650 coins (approximately $51,000) to a maximum of 9,000 coins (approximately $702,000).

According to The Information, TSMC (TSM.N) will develop AI chip packaging technology.In the past, packaging has been regarded as a relatively conventional process in semiconductor manufacturing, but with the surge in AI demand, chip design companies need to integrate more processors and high-bandwidth memory into increasingly large and complex packages. Advanced packaging has become one of the industry's most critical bottlenecks. Intel has developed a packaging technology called Embedded Multi-Die Interconnect Bridge (EMIB).This technology uses small silicon bridges to establish high-speed connections between processors and memory, enabling support for larger-scale multi-chip designs, thus creating more powerful AI chips and helping chip designers achieve supply chain diversification, which has attracted the attention of potential customers such as NVIDIA (NVDA.O).Insiders say that within TSMC, engineers refer to this advanced packaging project as "EMIB-like" and have discussed this solution with some customers.

Domestic DRAM storage IDM leader Changxin Technology will officially list on the Sci-Tech Innovation Board on July 27, with an issuance valuation of approximately 580 billion yuan and a total fundraising amount of 29.5 billion yuan, of which about 22.066 billion yuan is for equipment purchase and installation costs. Industry insiders believe that 2026-2027 is the golden window period for the introduction of domestic equipment.In terms of the supply chain, on the equipment side, North Huachuang has shipped a large volume of various categories such as etching and thin film deposition, Zhongwei Company continues to validate and mass-produce etching and thin film equipment, Huahai Qingshi CMP equipment has entered the core supply chain, and Jingce Electronics and Jingzhida testing equipment are benefiting simultaneously. On the materials side, Yake Technology precursor products cover advanced process needs, Guanggang Gas provides special gases and bulk gases, Jinhong Gas has a gas production order cycle of 15 years, Tongcheng New Materials ArF/KrF photoresists have entered mass production, Jingrui Electric Materials has a market share of over 40% in high-purity hydrogen peroxide, but high-end photoresists are still in the validation stage, and Debang Technology is in the sample testing stage. On the packaging and module side, Huatian Technology is a packaging supplier, Jiangbolong and Demingli have reached procurement agreements, while Maijie Technology is still in the introduction phase. On the distribution side, Shangluo Electronics has been authorized, and there are expectations for supply strategy adjustments after listing. Several listed companies hold shares indirectly through industrial funds, with Shangfeng Cement holding approximately 0.1517% of the equity before issuance.

The CEO of Mysten Labs, evan.sui, stated in a recent interview that he does not agree with the notion of "bear markets are great, keep building." In fact, bear markets are not "great" and are not worth celebrating or boasting about. The volatility does not merely "cleanse the market," but can scare away builders and users, leading to a smaller talent pool and slower adoption processes. While bear markets may allow a few teams to focus more, packaging it as beneficial for everyone overlooks the real costs and can harm the long-term development of the crypto industry. During downturns, many people lose their savings, cash flow breaks down, and even some strong teams may not be able to survive, which genuinely harms many individuals.

According to the Securities Times, Douyin released the "Douyin Community Financial Industry Convention (Trial)," which mentions, "It is prohibited to package and publish illegal financial content related to virtual currency exchange business, providing information intermediary and pricing services for virtual currency transactions under the concepts of blockchain, digital assets, etc.; it is prohibited to analyze or predict individual stock buying and selling prices, promote future trends, provide investment consulting advice, and other illegal stock recommendation behaviors in the name of popular science."

ChainCatcher news, according to The Block, CKpool developers revealed that the miner who packaged block height 899,826 early this morning is an independent miner using a hash power rental strategy. This miner temporarily increased their hash power from 6.11 PH/s to 261 PH/s through CKpool's solo mining software, ultimately successfully mining the block with a probability of about 1/3050 (when the total network hash power was 796 EH/s), earning a reward of 3.151 BTC (approximately $330,000).It is worth noting that this is the 300th block mined by an independent miner in CKpool's history. A similar case occurred in April this year, demonstrating the potential for small and medium miners to participate in Bitcoin mining through flexible strategies.

ChainCatcher News, U.S. Department of Commerce: The Biden-Harris administration launches a competition for up to $1.6 billion in funding to accelerate the development of advanced semiconductor packaging technology in the United States.

ChainCatcher news, the currency market of the Sui ecosystem, Scallop, announced that Scallop sCoins have now been wrapped and can be viewed in the Sui wallet. Scallopers will be able to migrate directly from the old version of sCoins to the newer Wrapped sCoins through the Scallop dApp.It is reported that sCoins are Scallop's liquidity derivative tokens.