Samsung Electronics adjusts the next-generation DRAM roadmap, naming B1b as D0a

According to a report by ZDNet Korea, Samsung Electronics is adjusting its next-generation DRAM strategy by incorporating the previously project-based B1b into its official roadmap, naming it the first DRAM D0a below 10 nanometers. Previously, D0a referred to vertical transistor DRAM, and this product is now classified separately as D0a-V. This renaming aims to accelerate the introduction of advanced packaging in general DRAM.

B1b will manufacture storage cells and peripheral driver circuits on different wafers before bonding them together, using wafer-to-wafer hybrid bonding and directly connecting through copper interconnects. The currently commercialized DRAM is 1c, which is the 6th generation 10 nanometer level, with a line width of about 11 to 12 nanometers; the next generation 1d is the 7th generation 10 nanometer level, with a line width of about 10 to 11 nanometers, considered effectively the last 10 nanometer level product, with the related line width being a marketing term rather than an actual physical size. Vertical transistors can arrange transistors within the cell vertically, reducing the cell area from 6F² to 4F², but they need to address high aspect ratio etching and leakage current, making development more challenging. Wafer-to-wafer hybrid bonding has already been mass-produced in CMOS image sensors and high-stacking NAND.

Samsung Electronics is evaluating the use of B1b for the 8th generation high bandwidth memory HBM5. HBM5 is expected to be mass-produced around 2029, aiming to increase operating speed by more than 50% compared to HBM4E. Industry estimates suggest that D0a DRAM based on B1b will be commercially available in about two years, with specific mass production investment schedules likely to be determined by mid-next year.