Samsung Electro-Mechanics proposed the direction of AI semiconductor substrate MLC integration

On September 10, Kim Sang-hoon, the head of the packaging division at Samsung Electro-Mechanics, delivered a speech at the KPCA Show International Seminar INSIGHT 2026 held at the Incheon Songdo Conference Center, proposing a multilayer core (MLC) technology direction to address the large-scale and high-multilayer challenges of AI semiconductor packaging substrates.

Kim Sang-hoon stated that in the past, the single-layer core (SLC) method, which increased the thickness of a single CCL, led to increased difficulty in processing internal vias and circuits as the core thickened, and the size of the vias became limited. The MLC approach shifts to a combination of CCL and PPG multilayers, or even a mixed structure of two CCLs, which can simultaneously enhance rigidity and wiring freedom, while also allowing for ground or signal wiring to be arranged in the PPG layer. A bonding layer added between the two CCLs can provide more stable support for the substrate, but the process is more complex.

Currently, the commonly used bump pitch in mass production is above 90μm, with around 85μm being the turning point for printed fine solder ball processes. The difficulty significantly increases around 80μm, and the 55-45μm range may shift towards metal bumps. Glass cores are another option, offering higher rigidity and lower thermal expansion coefficients, which help reduce warping in large packages, but issues related to fragility and micro-hole plating technology need to be addressed. The substrate must meet signal integrity, power integrity, and mechanical integrity requirements simultaneously, with high-performance packaging substrate layers expected to evolve from about 20 layers at the 90mm level to 120mm and even more than 40 layers.