3nm

According to the Industrial and Commercial Times, Japan's Ministry of Economy, Trade and Industry has approved TSMC's first phase plan for the production of advanced semiconductors using 3-nanometer process at its second factory in Kumamoto Prefecture. This will be the first time a manufacturer in Japan produces 3-nanometer chips. TSMC can further expand its production capacity based on additional support from the Japanese government. Kumamoto Prefectural Governor Seiji Kimura stated that this plan will drive a new wave of creative revitalization.The Nikkei reported that the Ministry of Economy has listed the Kumamoto second factory as a recipient of subsidies, with plans to produce 3-nanometer chips, expected to officially start production in December 2028, with final capacity depending on the amount of subsidies. The Ministry will include the budget needed for subsidies in the fiscal year 2027 budget request, with the Japanese government originally planning to provide 732 billion yen in subsidies. The Asahi Shimbun pointed out that the Kumamoto second factory is still under construction and is adjacent to the already operational Kumamoto first factory.Previously, TSMC planned for the second factory to manufacture 6-nanometer and 12-nanometer processes, with a monthly capacity of 48,000 wafers, and planned to produce 40-nanometer chips; in February this year, the plan was changed to 3-nanometer, reducing the monthly capacity to 6,000 wafers. The adjustment plan for the Kumamoto first factory was also approved by the Ministry, with the original plan to produce 55,000 wafers per month covering 22 to 28 nanometers and 12 to 16 nanometers, while the new plan stops production of 12 to 16 nanometers, changing to 45,000 wafers per month for 22 to 28 nanometers.

According to the Economic Daily, major companies such as Apple, NVIDIA, AMD, Qualcomm, and MediaTek are racing towards AI and high-performance computing, recently increasing their orders for TSMC's 2-nanometer family capacity by 10% to 20%. As a result, TSMC is accelerating the expansion of its 2-nanometer family, with progress exceeding expectations. TSMC has consistently refrained from commenting on customer information and market rumors.The market originally estimated that TSMC's monthly capacity for the 2-nanometer family would be around 90,000 to 100,000 wafers by the end of this year, with expectations for continued double-digit growth to reach 110,000 to 140,000 wafers by 2027. Industry sources indicate that due to strong customer demand, the monthly capacity is expected to surge to 120,000 wafers by the end of this year, achieving the originally set 2027 target ahead of schedule. Sources say that in response to the demands from Apple and non-Apple customers, the speed and scale of new capacity for the 2-nanometer family are setting new records, far exceeding the ramp-up speed of the 3-nanometer family in its first year.TSMC's Senior Vice President and Co-COO, Wei Chen-Hao, stated at this year's North America Technology Forum that in response to strong demand from AI and other sectors, there will be five 2-nanometer fabs ramping up simultaneously for the first time this year, including two in Hsinchu and three in Kaohsiung; the wafer output in the first year of 2-nanometer will increase by 45% compared to the first year of 3-nanometer in 2023; the compound annual growth rate of 2-nanometer capacity from 2026 to 2028 will reach 70%. TSMC's 3-nanometer capacity in the Southern Taiwan Science Park is expected to reach nearly 180,000 wafers per month in the fourth quarter of this year, and three new 3-nanometer fabs are being established in Taiwan, Arizona in the United States, and Japan. The second fab in the United States is planned to begin mass production in the second half of 2027.

As we enter the late third quarter of 2026, TSMC's 3nm and 2nm advanced process and CoWoS advanced packaging capacity continue to be in high demand. NVIDIA and Apple continue to dominate the resources for advanced processes and packaging; Amazon AWS's Annapurna has recently increased its AI self-developed chip production, securing more 3nm capacity. MediaTek, in addition to mobile chips, is also competing for 2/3nm process and CoWoS-S/L capacity with large orders related to Google TPU.There are reports that TSMC has recently readjusted its capacity allocation. After MediaTek secured a large order from Google TPU, the next-generation TPU v9 will simultaneously use TSMC's CoWoS-L and Intel's EMIB-T, which has slightly adjusted MediaTek's 3nm and 2nm capacity arrangements. Currently, TSMC's main customer for 3nm is NVIDIA, which is expected to surpass Apple to become the largest customer by 2025; the demand for 2nm is primarily from Apple and others. After AWS increased Annapurna's production, its 3nm and CoWoS configuration priority has improved.Starting in early 2026, TSMC will accelerate capacity expansion, with the 2nm monthly capacity of Hsinchu Baoshan Fab 20 and Kaohsiung Fab 22 reaching 50,000 wafers each by the end of October, totaling about 100,000 wafers; by the end of October, the monthly capacity for 3nm in Tainan Science Park is about 185,000 wafers. As of the end of September, the overall capacity utilization rate is about 96.2%, with 100% utilization for processes below 16/12nm down to 2nm. The shortage of CoWoS supply has driven advanced packaging orders to overflow, with the priority for orders going to ASE Group's Siliconware Precision Industries first, followed by Amkor, and Chipbond, among others. Chipbond's related testing and packaging capacity is fully loaded, with order visibility extending to 2028.

The supply chain reveals that TSMC has disclosed its expansion targets for 2/3 nanometers for the first time next year. The 2-nanometer production is expected to increase from 90,000 wafers at the end of this year to 110,000 wafers by mid-next year, an increase of 22%; the 3-nanometer production is expected to rise from over 180,000 wafers at the end of this year to 210,000 wafers by mid-next year, an increase of over 16%. TSMC did not comment on market rumors yesterday and emphasized that capacity-related statements are based on the company's announcements.It is reported that TSMC's monthly capacity for 3 nanometers reached 120,000 to 130,000 wafers at the end of last year and is expected to expand to 180,000 wafers by the end of this year, with a target of over 210,000 wafers by mid-next year. The monthly capacity for 2 nanometers is expected to reach 90,000 wafers by the end of this year. TSMC previously stated that capital expenditures in 2026 will range from $60 billion to $64 billion, with approximately 70% to 80% allocated for advanced processes, and plans to add three 3-nanometer fabs located in Taiwan, Arizona in the United States, and Japan, while converting 5-nanometer equipment in Taiwan to support 3-nanometer capacity.