2nm

According to a report by North Korea Biz on October 20, Samsung Electronics' foundry division has seen its 4-nanometer process capacity nearing full load due to an increase in customer orders, while the company is also expanding efforts to attract new customers for its 5-nanometer process. The report states that contracts for the most advanced 2-nanometer process with major global tech companies are still delayed, prompting Samsung to increase the utilization rates of its relatively stable 4-nanometer and 5-nanometer processes to improve profitability.The 4-nanometer process is used for smartphone application processors, artificial intelligence semiconductors, and high-performance computing chips. The report indicates that not all chips in the expanding artificial intelligence semiconductor market require the most advanced processes; the manufacturing costs of 4-nanometer and 5-nanometer processes are relatively low while still achieving high performance, making them suitable for certain artificial intelligence inference chips and application-specific integrated circuits.Regarding the 2-nanometer process, Samsung is in discussions with major global tech companies about production contracts, but some negotiations are taking longer than originally expected. In addition to yield rates, the most advanced processes also require comprehensive verification of energy efficiency, design assets, and stable mass production capabilities, which means a longer time frame from contract signing to mass production. Samsung views the 2-nanometer process as the core growth driver for its next-generation foundry business and plans to continue using the fully surrounded gate transistor structure first introduced in the 3-nanometer process to improve energy efficiency and performance.

According to the Economic Daily, major companies such as Apple, NVIDIA, AMD, Qualcomm, and MediaTek are racing towards AI and high-performance computing, recently increasing their orders for TSMC's 2-nanometer family capacity by 10% to 20%. As a result, TSMC is accelerating the expansion of its 2-nanometer family, with progress exceeding expectations. TSMC has consistently refrained from commenting on customer information and market rumors.The market originally estimated that TSMC's monthly capacity for the 2-nanometer family would be around 90,000 to 100,000 wafers by the end of this year, with expectations for continued double-digit growth to reach 110,000 to 140,000 wafers by 2027. Industry sources indicate that due to strong customer demand, the monthly capacity is expected to surge to 120,000 wafers by the end of this year, achieving the originally set 2027 target ahead of schedule. Sources say that in response to the demands from Apple and non-Apple customers, the speed and scale of new capacity for the 2-nanometer family are setting new records, far exceeding the ramp-up speed of the 3-nanometer family in its first year.TSMC's Senior Vice President and Co-COO, Wei Chen-Hao, stated at this year's North America Technology Forum that in response to strong demand from AI and other sectors, there will be five 2-nanometer fabs ramping up simultaneously for the first time this year, including two in Hsinchu and three in Kaohsiung; the wafer output in the first year of 2-nanometer will increase by 45% compared to the first year of 3-nanometer in 2023; the compound annual growth rate of 2-nanometer capacity from 2026 to 2028 will reach 70%. TSMC's 3-nanometer capacity in the Southern Taiwan Science Park is expected to reach nearly 180,000 wafers per month in the fourth quarter of this year, and three new 3-nanometer fabs are being established in Taiwan, Arizona in the United States, and Japan. The second fab in the United States is planned to begin mass production in the second half of 2027.

On September 15, MediaTek announced the next-generation flagship chip, Dimensity 9600 Pro, at the 2026 Dimensity flagship product launch event. According to the official introduction, this chip is manufactured using TSMC's 2nm process, with over 33 billion transistors.The chip adopts a heterogeneous computing architecture that integrates CPU, GPU, NPU, ISP, and other computing cores, with AI as the core engine. It features an all-large-core architecture, equipped with dual super-large cores C2-Ultra at 4.55GHz, three large cores C2-Pro at 4.35GHz, and three large cores C2-Pro at 3.1GHz, along with 34.5MB of L2+L3+system cache, supporting LPDDR6 memory and UFS 5.0 flash storage. Compared to Dimensity 9500, the power consumption of the super-large cores has decreased by 37%, and the multi-core power consumption has decreased by 61%.In GeekBench V6.4, it scored 4276 points in single-core and 12650 points in multi-core, representing an improvement of about 17% in single-core and about 15% in multi-core compared to Dimensity 9500. The NPU adopts a dual NPU architecture, equipped with APU 1090, with peak performance improved by 51%. MediaTek claims to have maintained the number one position in global smartphone SoC market share for six consecutive years.

The supply chain reveals that TSMC has disclosed its expansion targets for 2/3 nanometers for the first time next year. The 2-nanometer production is expected to increase from 90,000 wafers at the end of this year to 110,000 wafers by mid-next year, an increase of 22%; the 3-nanometer production is expected to rise from over 180,000 wafers at the end of this year to 210,000 wafers by mid-next year, an increase of over 16%. TSMC did not comment on market rumors yesterday and emphasized that capacity-related statements are based on the company's announcements.It is reported that TSMC's monthly capacity for 3 nanometers reached 120,000 to 130,000 wafers at the end of last year and is expected to expand to 180,000 wafers by the end of this year, with a target of over 210,000 wafers by mid-next year. The monthly capacity for 2 nanometers is expected to reach 90,000 wafers by the end of this year. TSMC previously stated that capital expenditures in 2026 will range from $60 billion to $64 billion, with approximately 70% to 80% allocated for advanced processes, and plans to add three 3-nanometer fabs located in Taiwan, Arizona in the United States, and Japan, while converting 5-nanometer equipment in Taiwan to support 3-nanometer capacity.

According to South Korea's "Cultural Daily," Samsung Electronics' wafer fab in Taylor, Texas, is expected to enter trial operation around the end of this month, as orders for 2-nanometer chips from Tesla, Broadcom, Arm, and others continue to pour in, with pre-production capacity nearing full load. The plant has accumulated an investment of $37 billion since 2022, with plans to begin trial operation early next month and mass production next year, with an initial monthly capacity of about 50,000 wafers, close to TSMC's approximately 80,000 wafers.The report states that the Taylor plant will produce Tesla's next-generation artificial intelligence chip AI5, Broadcom's new generation communication chips, and Arm's smart device AI chips, among others. Samsung's 2-nanometer yield has increased from about 60% earlier this year to around 80% recently. The company sent personnel for process, equipment, and yield to the plant in June, and began installing equipment in July. At a recent earnings meeting, Samsung projected that this year's 2-nanometer order volume would more than double compared to last year, and stated that NVIDIA's inference chip Grok3 began mass production last month; Samsung also recently raised the foundry price for 4-nanometer chips by up to 15%.The second Taylor plant is scheduled to start construction by the end of this year and begin mass production in 2030. Samsung has requested major partners to complete the relevant production equipment safety certifications in advance, and some partners are considering sending dozens of personnel to the local area. At the same time, Intel issued about $20 billion in new shares last month and expanded investments in 2-nanometer level 18A and 1.4-nanometer level 14A, while Japan's Rapidus completed its 2-nanometer factory in Hokkaido last month and entered the wafer trial production stage.

According to South Korean media ZDNet Korea, Samsung Electronics is adjusting the original purpose of its NRD-K Line 2 at the Giheung campus from a research and development facility to a wafer foundry line, with the main target product being the 2nm base chips required for NVIDIA's HBM. This production line is expected to be operational in the second half of 2028, adopting a "Send-Fab" model, which involves receiving wafers from other mass production lines and performing specific processes.NRD-K is the most advanced composite research and development campus built by Samsung Electronics to seize future semiconductor technology, with a total investment of approximately 20 trillion won, planning for three production lines, of which the first line is scheduled to be completed by the end of 2024. This adjustment aims to proactively respond to the expansion of HBM demand driven by investments in AI infrastructure. Samsung plans to first apply the 2nm process to custom HBM and HBM5 to maintain performance advantages.Industry insiders point out that the scale of NRD-K Line 2 is relatively small, making it suitable for operation in the Send-Fab format. However, there are still about two years until the production line is operational, and the final purpose may be adjusted again based on market conditions. Samsung had previously considered using this production line for DRAM production, but after modifications to the relevant plans this month, DRAM capacity will be more concentrated in the Pyeongtaek campus. Equipment procurement orders have not yet been officially issued.