hbm4e

TrendForce reported on October 12, citing Chosun Biz, that as AI packaging accommodates more computing and storage chips, the intermediary layer connecting computing chips and HBM is expected to significantly increase in size, making next-generation HBM cooling more important. Samsung Electronics is preparing multiple technologies to address the cooling challenges of HBM4E, which is scheduled to begin mass production next year.Currently, the area of the AI intermediary layer is about 5.5 times the maximum exposure area of 858 square millimeters of an EUV lithography machine. Semiconductor equipment industry insiders expect that the intermediary layer carrying HBM could expand to 9 times, 12 times that area, and ultimately about 40 times. Reasons include limitations in process miniaturization and the popularity of chiplet-style 2.5D packaging, where multiple computing chiplets and HBM stacks are placed on the same intermediary layer, making it difficult for a single advanced process chip to meet AI computing power demands.Samsung is considering hybrid copper bonding and thermal path blocks. The former replaces the micro bumps between stacked DRAM chips with direct copper-to-copper connections, which can reduce inter-layer gaps, make the stack thinner, and improve heat dissipation, a technology Samsung showcased at NVIDIA GTC in March 2026. The thermal path block establishes a dedicated thermal path in the D2D PHY area responsible for high-speed transmission between HBM base chips and GPUs, which Samsung is validating with HBM4E and plans to implement in HBM5. According to ETNews, SK Hynix's iHBM places high thermal conductivity but electrically insulating cooling materials around the heat-concentrated D2D PHY, which is expected to reduce thermal resistance by about 30%.

According to the Korea Economic Daily, Samsung Electronics' next-generation high-bandwidth memory "12-layer HBM4E" product has passed quality verification by Nvidia and major hyperscale data center operators.

According to a report by Seoul Economic Daily, Samsung Electronics plans to increase the production of the sixth-generation high bandwidth memory HBM4 and the seventh-generation HBM4E, among other HBM4 series, by at least more than double compared to this year. The company intends to outsource the cleaning volume of glass substrates required for thinning HBM DRAM from 20,000 pieces per month this year to 50,000 pieces per month next year, an increase of 2.5 times compared to this year. Last year, the monthly demand for these substrates was about 10,000 pieces, which has already doubled this year compared to last year.The HBM4 and HBM4E that Samsung Electronics is focusing on expanding production are primarily high-stacking products with 12 layers or more. The company began mass production and shipment of HBM4 using sixth-generation 10nm (1c) DRAM and 4nm process-based chips in February this year, and provided 12-layer samples of HBM4E to customers such as Nvidia in May. The industry expects that, based on monthly wafer input, Samsung Electronics' HBM production capacity will increase from about 180,000 pieces this year to about 250,000 pieces next year, an increase of nearly 40%; the shipment proportion of the HBM4 series may rise from about 40% this year to about 80% next year.

According to South Korean media reports, Samsung Electronics is cooperating with Nvidia (NVDA.O) to develop 8-layer seventh-generation high bandwidth memory (HBM4E), significantly reducing the stacking height compared to the original plans of 12 layers and 16 layers. The speed specification proposed by Nvidia is 17-18Gbps, which is about 20% higher than Samsung's initial HBM4E sample speed of 14.4Gbps. This product is reported to be used for NVHBM.

According to reports from Seoul Economic Daily, Samsung Electronics is developing HBM4E (seventh generation) 8-layer products that meet NVIDIA's requirements, aiming to secure its position as a core partner in the supply of customized high-bandwidth memory NVHBM. This product reduces the stacking height compared to the originally planned 12-layer and 16-layer designs. The speed specifications proposed by NVIDIA are 17-18Gbps, which is about 20% higher than the speed of Samsung's initial HBM4E samples (14.4Gbps), and will be used for NVIDIA's publicly disclosed NVLink optimized specifications for NVHBM.The use of 8 layers, contrary to the previous logic of increasing capacity by adding more stacking layers in HBM, can reduce the difficulty of post-processing and yield pressure, which is beneficial for expanding supply and is seen as NVIDIA's strategy to alleviate memory shortages. NVHBM is expected to be applied starting with the next-generation AI GPU "Rubin Ultra," which is set to launch next year. This GPU will expand the interconnection scale between GPUs from a maximum of 72 to 576, enhancing overall computing power through hundreds of GPUs equipped with faster HBM.In the customized HBM market, Samsung is more competitive compared to SK Hynix and Micron, as NVHBM requires DRAM and the production capabilities of logic chip-based bare die designs, which Samsung can integrate. Industry insiders say that Samsung has verified the highest speed levels in HBM4, which can provide an advantage in speed competition.