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first_img The shortage of storage chips impacts the smartphone market, with shipments in the third quarter hitting a 14-year low for the same period

Financial Associated Press reported on October 12, citing market research firm Counterpoint Research, that the ongoing construction of artificial intelligence infrastructure continues to squeeze the supply of storage chips, putting pressure on costs and supply in consumer electronics. Preliminary data shows that global smartphone shipments in the third quarter of 2026 are expected to decline by 20% year-on-year, reaching the lowest level for the same period since 2012. The storage chip crisis has impacted the smartphone market for the second consecutive quarter, with rising chip costs increasing the overall bill of materials, leading manufacturers to raise retail prices. Since 2026, global smartphone retail prices have cumulatively increased by about 20%.Samsung remains the global leader, with its market share rising to 23% in the third quarter, although shipments declined by 3% year-on-year, marking the largest share increase among major manufacturers. Apple's share rose to 22%, marking its first time surpassing 20% in the third quarter, but shipments declined year-on-year. The absence of the base model iPhone 18 this year resulted in a lower channel distribution scale in the first month of new product launches compared to the previous year's iPhone 17 series. The iPhone 18 Pro series performed better than its predecessor in China and India.Xiaomi's shipments in the third quarter declined by over 30% year-on-year, with its market share dropping to 10%. Both OPPO and vivo saw their shipments decline by over 20% year-on-year, with shares falling to 9% and 8%, respectively. Counterpoint senior analyst Shilpi Jain stated that consumers are holding onto their existing devices for longer and are considering more refurbished devices. Counterpoint indicated that global smartphone shipments are unlikely to see a significant recovery before improvements in storage chip costs and supply.

first_img Avalanche stated that the South Korean KSD platform will support its ledger, with Samsung SDS aiming for completion in February 2027

Avalanche announced on October 13 that the Korean Securities Depository (KSD) is "building infrastructure connections based on Avalanche" for the Korean securities tokenization market. KSD's technical guidelines confirm that Avalanche is one of several ledger technologies supported by its platform plan; Avalanche's post states that the plan covers issuance, trading, clearing, settlement, and investor rights, ultimately achieving on-chain settlement.KSD's distributed ledger guidelines (reflecting development as of July 2026) place Avalanche alongside Hyperledger Besu and Hyperledger Fabric, committing to support multiple ledger technologies rather than positioning Avalanche as the sole option for Korean securities infrastructure. The project has transitioned from a testing ground to the construction phase of a production platform, with Samsung SDS winning the bid to build it, aiming to convert the technology testing platform into a system that supports real transactions and stable operations, with a target completion date of February 2027.The roadmap released by the Korean Financial Services Commission in September shows that the revised terms for recognizing tokenized securities will take effect on February 4, 2027, with the first phase launching in the same month, initially covering private money market funds and bonds aimed at institutional investors, non-listed stocks held through trust structures, and publicly issued fractional investment securities. The second phase will expand to all publicly issued securities. On-chain payments related to stablecoins belong to the final phase, and the commission remains flexible on the timing for the second and third phases, setting November 11 as the deadline for public consultation on the implementation regulations.

first_img Samsung Electronics plans three models of zNAND, aimed at customized AI storage

According to a report by ZDNet Korea on October 12, Samsung Electronics is expanding the application range of the next-generation NAND flash memory zNAND and plans to subdivide the products into three types: zNAND-O, zNAND-T, and zNAND-I, in addition to the publicly announced zNAND-O. The report states that Samsung Electronics has not officially announced the latter two products, but the industry has learned that related plans have entered the early development stage to address the increasing demand for customized storage in AI infrastructure.zNAND-O is aimed at edge AI. Unlike traditional wire bonding, this solution vertically stacks NAND in 4 or 8 layers through silicon vias, shortening the data transmission path and enhancing speed and energy efficiency. Samsung Electronics first publicly showcased the zNAND-O model at a memory-related event in the United States in August this year.zNAND-T focuses on throughput and is aimed at high-capacity, high-performance AI data centers, also expanding bandwidth through vertical stacking and silicon vias, and is referred to by the industry as high-bandwidth flash memory. zNAND-I focuses on increasing input/output operations per second, used for frequent processing of small-capacity temporary data such as key-value caches in AI inference. The report also mentions that SK Hynix is developing AI NAND product series such as AIN P, AIN D, and AIN B.

first_img Samsung and SK Hynix respond to HBM4E heat dissipation, AI intermediary layer may expand to 40 times

TrendForce reported on October 12, citing Chosun Biz, that as AI packaging accommodates more computing and storage chips, the intermediary layer connecting computing chips and HBM is expected to significantly increase in size, making next-generation HBM cooling more important. Samsung Electronics is preparing multiple technologies to address the cooling challenges of HBM4E, which is scheduled to begin mass production next year.Currently, the area of the AI intermediary layer is about 5.5 times the maximum exposure area of 858 square millimeters of an EUV lithography machine. Semiconductor equipment industry insiders expect that the intermediary layer carrying HBM could expand to 9 times, 12 times that area, and ultimately about 40 times. Reasons include limitations in process miniaturization and the popularity of chiplet-style 2.5D packaging, where multiple computing chiplets and HBM stacks are placed on the same intermediary layer, making it difficult for a single advanced process chip to meet AI computing power demands.Samsung is considering hybrid copper bonding and thermal path blocks. The former replaces the micro bumps between stacked DRAM chips with direct copper-to-copper connections, which can reduce inter-layer gaps, make the stack thinner, and improve heat dissipation, a technology Samsung showcased at NVIDIA GTC in March 2026. The thermal path block establishes a dedicated thermal path in the D2D PHY area responsible for high-speed transmission between HBM base chips and GPUs, which Samsung is validating with HBM4E and plans to implement in HBM5. According to ETNews, SK Hynix's iHBM places high thermal conductivity but electrically insulating cooling materials around the heat-concentrated D2D PHY, which is expected to reduce thermal resistance by about 30%.

first_img Reports say Samsung phones will reduce production by up to 30% in the fourth quarter of 2026

IT Home cited a report from Money Today on October 8, stating that Samsung Electronics' Mobile Experience (MX) division plans to cut smartphone production, with a maximum reduction of 30% in the fourth quarter of 2026. Several IT industry insiders have indicated that Samsung's MX division has notified multiple partners to reduce product supply by 20% to 30%. IT Home noted that the original text did not specify whether this 30% is compared to the previous quarter, year-on-year, or against earlier expected production.In terms of production, Samsung Electronics originally planned to rely on new products like the Galaxy Z Fold8 to produce up to 270 million smartphones for the year. After the significant reduction in the fourth quarter, the final annual production is expected to drop to just over 200 million units, exceeding market expectations. IDC data shows that smartphone shipments in the first and second quarters of this year were 62.4 million and 62.7 million units, respectively, with previous forecasts predicting shipments of 59 million and 52 million units for the third and fourth quarters, indicating a decline of about 12% in the fourth quarter compared to the third quarter.Money Today reported that the rise in memory prices is the core driving factor behind the production cuts. TrendForce data shows that the price of 12GB low-power DRAM (LPDDR5X) for smartphones was $145 to $146 in the second quarter of this year, an increase of 175% compared to the same period last year. The report also stated that demand for artificial intelligence has driven up memory prices, with smartphone DRAM prices expected to rise by about 20% in the third quarter, reaching as high as $180. IT industry insiders stated that Samsung's current smartphone sales are no longer profitable, and the production cuts are a strategy to maintain overall profitability.

first_img AMD CEO Lisa Su visits Samsung again, stating that they will discuss broader cooperation

AMD Chairwoman and CEO Lisa Su arrived at Samsung Electronics' Seocho office building in Seoul at around 4:44 PM on October 7, meeting with Vice Chairman Choi Yong-hyun, head of the Device Solutions Division, approximately seven months after her last visit to South Korea. Jack Huynh, head of AMD's Computing and Graphics Group, and Vice President Joseph Macri accompanied her. Lisa Su stated that both sides would discuss a broader partnership and mentioned that Samsung has many partners; when asked if she would meet with Lee Jae-yong, she said it was inconvenient to disclose.Before visiting Samsung, Lisa Su attended AMD Player Day in Seoul, referring to Samsung and SK Hynix as core supply chain partners and stating that they are planning a long-term supply chain due to rising demand for artificial intelligence. She mentioned that the next-generation MI455 and Helios systems have begun shipping and both use HBM4, supported by two companies, and that the HBM collaboration will not stop at one generation. Reports indicate that the Instinct MI455X features 432GB of HBM4, an increase of 50% compared to the previous generation MI355X's 288GB of HBM3E. She noted that memory supply is very tight and that they are optimizing usage with customers and asking partners to expand production. TrendForce predicted on the 29th of last month that the limited advanced process capacity shared between HBM and regular DRAM may continue to lead to tight supply into next year.Reports state that both parties signed a memorandum of understanding in March this year centered on the supply of HBM4 and next-generation DDR5, designating Samsung as the main supplier of HBM4 for the MI455X and discussing Samsung's contract manufacturing of AMD's next-generation products. Choi Yong-hyun stated at that time that Samsung can provide memory, foundry, and packaging simultaneously.

first_img Samsung Electronics executive: It is expected that HBM will account for nearly 30% of DRAM wafer production capacity next year

According to a report by the Financial Associated Press citing local media on September 29, Samsung Electronics Executive Vice President Kim Taewoo stated that HBM is expected to account for nearly 30% of the total wafer capacity of DRAM manufacturers next year, up from the current ratio of about 20%. He mentioned that HBM competes with traditional DRAM for the same batch of wafer capacity, and increasing HBM output may squeeze the supply of traditional DRAM.TrendForce previously predicted that by the end of 2027, the HBM wafer input from the three major global HBM suppliers will account for about 30% of the total DRAM wafer input, but in terms of storage capacity, it will only contribute about 13% of the total DRAM supply. Additionally, according to media reports on September 20, Samsung began mass production and shipment of HBM4 in February this year and provided 12-layer HBM4E samples to customers including NVIDIA in May; the industry expects Samsung's monthly wafer input for HBM to increase from about 180,000 wafers this year to about 250,000 wafers next year.On the same day, TrendForce stated that the demand for AI servers continues, and HBM and general DRAM will still share limited advanced process capacity. The storage supply will remain tight in 2027, and the price expectations for HBM in 2027 have been raised, with an expected year-on-year increase of 121% in the mixed average selling price. Due to limited supply and rising system costs, 8-layer HBM is expected to become a priority evaluation option for several manufacturers in 2027, with its price per Gb expected to be about 10% to 20% higher than that of 12-layer products.

first_img Central Daily News: Former CEO of Changxin Storage accused of pressuring for Samsung technology

According to a report by South Korea's "JoongAng Ilbo," a statement obtained from a former head of equipment investment at Changxin Memory Technologies (CXMT), who has a background at Samsung Electronics, reveals that the former CEO of CXMT, Wang Ningguo, summoned the Korean team, including the individual in question, from October to December 2016. He demanded they bring back Samsung Electronics' Process Recipe Plan (PRP) and equipment information, threatening to report them to the South Korean government if they failed to do so, and warned them to verify their connections and not to lie. The individual stated that they felt scared at the time. The report mentioned that CXMT's management referred to Samsung Electronics as "Huangshan."After working at Samsung Electronics for 28 years, the individual joined CXMT and was prosecuted for allegedly leaking and using Samsung's 1.6 trillion won investment in the world’s first 18-nanometer DRAM process without authorization. In April of this year, they were sentenced to seven years in prison in the first trial and are currently in the second trial. The PRP includes the sequence of about 600 steps in DRAM manufacturing, equipment, condition values, and the companies and models of the equipment. Park, a former process design engineer at Samsung, hand-copied the relevant content into a 12-page notebook in September 2016 and brought it out, and is currently under an Interpol Red Notice.During the court hearing, the individual stated that there was a claim made during communications with the Chinese side that investment would not be provided to CXMT if they could not produce the 18-nanometer process. They later learned that the other party had wanted the technology from the very beginning, and CXMT initially had no plans to develop it independently. The pressure mentioned occurred before a meeting to prepare for the investment application. CXMT was established in 2016 with an investment of 14.4 billion yuan from Hefei Industrial Investment, a subsidiary of the Hefei municipal government, and had not been profitable for about 10 years, achieving its first annual profit last year with a net profit of 7.1 billion yuan.

first_img Samsung Electronics accelerates the construction of the first mass production line in Pyeongtaek P5, with the equipment introduction target moved up to the second quarter of next year

According to a report by ZDNet Korea on September 28, Samsung Electronics is accelerating the construction of the first mass production line (Ph1) at the Pyeongtaek Fifth Campus (P5) and is discussing with major equipment manufacturers to move the target for Ph1 equipment installation from the originally planned third quarter of next year to the second quarter of next year. P5 is the next-generation semiconductor production base aimed to be operational by 2028, and the construction of the Ph1 cleanroom began in the third quarter of this year.Samsung Electronics had previously advanced the completion of the P5 Ph1 cleanroom, originally scheduled for early next year, by about six months, so the equipment installation is expected around the third quarter of next year. Industry insiders say that the start time for equipment installation is planned to be moved up from July to August next year to around May to June next year; others have indicated that Samsung has even proposed to deliver equipment in the first quarter of next year for temporary storage at other locations, showing a strong willingness to invest early.Discussions on the investment for the second phase of P5 (Ph2) are also progressing. Currently, Ph1 is more likely to be built as a DRAM and HBM production line, while Ph2 is more likely to be built as an advanced NAND production line, including the tenth generation (V10). Equipment industry insiders say that formal purchase orders have not yet been placed, but Samsung has discussed building Ph2 as a NAND production line with partners, and due to the long equipment delivery cycle, they are requesting to prepare relevant components in advance. Reports indicate that large global tech companies are increasing orders for high-performance DRAM and NAND for AI infrastructure, while storage companies like Samsung have limited production capacity. Samsung stated during the second quarter earnings call in July that unmet demand this year will extend into next year, and the supply shortage next year will be more severe than this year, with shortages expected to continue until 2028.

first_img Samsung Electronics adjusts the next-generation DRAM roadmap, naming B1b as D0a

According to a report by ZDNet Korea, Samsung Electronics is adjusting its next-generation DRAM strategy by incorporating the previously project-based B1b into its official roadmap, naming it the first DRAM D0a below 10 nanometers. Previously, D0a referred to vertical transistor DRAM, and this product is now classified separately as D0a-V. This renaming aims to accelerate the introduction of advanced packaging in general DRAM.B1b will manufacture storage cells and peripheral driver circuits on different wafers before bonding them together, using wafer-to-wafer hybrid bonding and directly connecting through copper interconnects. The currently commercialized DRAM is 1c, which is the 6th generation 10 nanometer level, with a line width of about 11 to 12 nanometers; the next generation 1d is the 7th generation 10 nanometer level, with a line width of about 10 to 11 nanometers, considered effectively the last 10 nanometer level product, with the related line width being a marketing term rather than an actual physical size. Vertical transistors can arrange transistors within the cell vertically, reducing the cell area from 6F² to 4F², but they need to address high aspect ratio etching and leakage current, making development more challenging. Wafer-to-wafer hybrid bonding has already been mass-produced in CMOS image sensors and high-stacking NAND.Samsung Electronics is evaluating the use of B1b for the 8th generation high bandwidth memory HBM5. HBM5 is expected to be mass-produced around 2029, aiming to increase operating speed by more than 50% compared to HBM4E. Industry estimates suggest that D0a DRAM based on B1b will be commercially available in about two years, with specific mass production investment schedules likely to be determined by mid-next year.
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