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first_img South Korean media: China's semiconductor industry is being promoted by a team system involving government, banks, and enterprises

According to South Korea's "JoongAng Ilbo," China's semiconductor industry is organized through collaboration among the central government, local governments, state-owned financial institutions, and enterprises, forming a system for fundraising, factory construction, and infrastructure support. The China National Integrated Circuit Industry Investment Fund has a first phase of 138.7 billion RMB, a second phase of 204 billion RMB, and a third phase of 344 billion RMB, totaling 686.7 billion RMB, with investments in companies such as SMIC, Hua Hong Semiconductor, and Yangtze Memory Technologies.Changxin Memory, established for 10 years, has risen to fourth in global DRAM market share, with a net loss of 21.13 billion RMB over the past three years, while R&D and equipment investments during the same period reached 185.2 billion RMB, with Hefei's state-owned capital providing about 80% of the funding for early projects. South Korea's Samsung Electronics and SK Hynix are responsible for investments, employment, technology development, and support for partners. The South Korean government plans to guide 622 trillion KRW in private investment by 2047 and provide 17 trillion KRW in low-interest loans and 1.1 trillion KRW in semiconductor ecosystem funds, but most of the burden will fall on enterprises.Park Kyung-soo, Executive Vice President of the Korea Semiconductor Industry Association: The semiconductor industry will fall behind in the next upturn if investment stops; even during downturns, R&D, equipment investment, and orders for materials and components must be maintained, requiring long-term policy, financial, and tax support. China is catching up with a national-level support system, and South Korea also needs a response system involving the government, political circles, financial institutions, and enterprises to act together.

first_img CXMT has launched the equipment bidding for the new factory in Shanghai and is planning to expand production in multiple locations

China's largest DRAM manufacturer Changxin Storage (CXMT) has recently launched a bidding for equipment from partners for its new factory in Shanghai and is advancing capacity expansion in multiple locations. CXMT is currently mass-producing DRAM in Hefei Phase II and Beijing Phase I, with an estimated capacity of about 200,000 wafers per month, which may exceed 300,000 wafers per month by the end of the year.CXMT plans to open the new factory in Shanghai in the fourth quarter of this year, and the related equipment bidding has already started. Semiconductor equipment industry insiders say that the factory is planned to be expanded in two phases, with capacity significantly exceeding 100,000 wafers per month. Subsequently, there are plans to open a new factory in Hefei in the first half of next year and the earliest new factory in Beijing in the second half of next year, with another new factory in Hefei opening in the first half of the year after next.Equipment industry insiders say that CXMT has communicated with multiple parties regarding the timing of building factories in various locations. If all plans are realized, CXMT could add at least 70,000 to 80,000 wafers of capacity per month each year from this year until 2028, with a long-term goal of exceeding 600,000 wafers per month. Samsung Electronics and SK Hynix's DRAM capacities are estimated at about 700,000 wafers and 600,000 wafers per month, respectively.

first_img Samsung Electro-Mechanics proposed the direction of AI semiconductor substrate MLC integration

On September 10, Kim Sang-hoon, the head of the packaging division at Samsung Electro-Mechanics, delivered a speech at the KPCA Show International Seminar INSIGHT 2026 held at the Incheon Songdo Conference Center, proposing a multilayer core (MLC) technology direction to address the large-scale and high-multilayer challenges of AI semiconductor packaging substrates.Kim Sang-hoon stated that in the past, the single-layer core (SLC) method, which increased the thickness of a single CCL, led to increased difficulty in processing internal vias and circuits as the core thickened, and the size of the vias became limited. The MLC approach shifts to a combination of CCL and PPG multilayers, or even a mixed structure of two CCLs, which can simultaneously enhance rigidity and wiring freedom, while also allowing for ground or signal wiring to be arranged in the PPG layer. A bonding layer added between the two CCLs can provide more stable support for the substrate, but the process is more complex.Currently, the commonly used bump pitch in mass production is above 90μm, with around 85μm being the turning point for printed fine solder ball processes. The difficulty significantly increases around 80μm, and the 55-45μm range may shift towards metal bumps. Glass cores are another option, offering higher rigidity and lower thermal expansion coefficients, which help reduce warping in large packages, but issues related to fragility and micro-hole plating technology need to be addressed. The substrate must meet signal integrity, power integrity, and mechanical integrity requirements simultaneously, with high-performance packaging substrate layers expected to evolve from about 20 layers at the 90mm level to 120mm and even more than 40 layers.

first_img TSMC's 1.4 nanometer factory in the Central Science Park is accelerating fully, with mass production expected in the second half of next year

The Central Science Management Bureau confirmed on the 9th that TSMC's Central Science Phase II 1.4 nanometer factory expansion is fully accelerating. The first P1 factory has completed its steel structure and is expected to begin trial production in April next year, with mass production anticipated in the second half of next year, ahead of the originally scheduled mass production in 2028. TSMC has applied to the Central Science Management Bureau to set up two temporary offices at the site, which are expected to be completed in April next year, with the first batch of over 5,400 operational and outsourced personnel moving in.The advanced process new factory for TSMC's Central Science Phase II park broke ground last October, planning to build four 1.4 nanometer factories, with nearly 2,000 workers working day and night. The P1 factory is currently undergoing floor and exterior wall construction, with the factory building expected to be completed early next year. The P2 factory has begun basic construction and is scheduled to be completed in October next year, with both factories expected to start mass production successively next year. The P3 factory has obtained a construction permit, while the P4 factory is in the process of applying for a construction permit, planning to be built with a six-month gap. P3 is expected to be completed in the second quarter of 2028, and P4 is scheduled for completion in the fourth quarter of the same year. After the P2 factory is completed in the second half of next year, an additional 1,000 operational personnel will be added, with the total number of employees expected to be between 9,000 and 10,000 when all four new factories in Phase II are completed and put into production.
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