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first_img Google disassembles retired servers to recycle DDR4 in response to memory shortages

Google's Senior Director of Supply Chain Infrastructure, Nikhil Cherian, revealed that to overcome memory bottlenecks, Google is developing software and hardware solutions and dismantling retired servers to recycle DDR4 components to establish an internal recycling supply chain. Google has designed special hardware adapters to connect the previous generation DDR4 to the new generation of AI servers while importing retired servers to remove their DDR4 modules for recycling.Cherian stated that the AI industry has rapidly shifted from being compute-constrained to memory-constrained, with high-performance memory accounting for about 75% of the bill of materials cost for a given AI server. A Goldman Sachs report indicated that memory prices will continue to rise in the third quarter, with personal computer DRAM prices expected to increase by 18% to 23% and server DRAM prices expected to rise by 13% to 18%. Trendforce data shows that in August, the spot market prices for DDR4 8GB and DDR5 8GB rose to $142 and $133, respectively.The two TPU ASICs launched by Google this year have been optimized for memory design, claiming to reduce memory demand to one-sixth of the original. The TPU8i chip features a dedicated layered memory design that relies on a high-speed DDR5 memory architecture to perform host-level tasks, with each chip equipped with 288GB of HBM3e high-bandwidth memory.

first_img Google claims that the cost of AI server memory has exceeded 75%, promoting a dual-track strategy for software and hardware

The SEMICON Taiwan 2026 Memory Summit took place on the 1st, where Nikhil Cherian, Senior Director of Supply Chain Infrastructure at Google Cloud under Alphabet, pointed out that with the popularity of multimodal and mixed expert architectures, AI computation has shifted from being power-limited to memory-limited, with high-performance memory accounting for over 75% of the cost of AI server hardware bill of materials. In the face of capacity, bandwidth, and power consumption bottlenecks, Google is breaking through the AI memory bottleneck through a dual-track strategy of hardware offloading for inference and training, and lossless quantization software algorithms.Google adopts an offloading strategy in hardware architecture, launching TPU 8i for low-latency inference and TPU 8t specialized for large-scale training. The TPU 8i is equipped with 288 GB of high-bandwidth memory, with SRAM capacity on the chip increased threefold to 384 MiB, placing dynamic conversation states and key-value caches on the chip itself to achieve zero chip-off latency. The TPU 8t forms a super-large computing cluster with 9600 chips, achieving a shared pool of HBM at a scale of 2 PB, eliminating chip-off data transfer bottlenecks, along with TPU Direct Storage technology.Google has developed the training-free TurboQuant lossless quantization algorithm, compressing the key-value cache of large models from 32 bits to 3 bits, reducing memory usage by six times without loss of accuracy, resulting in an eightfold acceleration in attention computation, and integrating old-generation DRAM technology to extend the lifecycle of components.

first_img Rising Sun Technology Holdings receives additional advanced packaging and testing orders from Google TPU and Intel

According to a report by the Economic Daily, ASE Technology Holding benefited from the increased capacity of Google TPU, significantly adding advanced packaging and testing orders. Intel is accelerating the promotion of its EMIB advanced packaging platform while simultaneously expanding its outsourcing orders to ASE Technology Holding, with the previously raised testing quotes showing benefits. Google continues to increase its AI capital expenditures to expand data centers, using TPU to support the Gemini large model, AI agents, and Google Cloud services. The market estimates that Google TPU will enter a large-scale production phase by 2028, with shipments expected to reach 12 to 15 million units. ASE Technology Holding has mastered 2.5D, 3D advanced packaging, and high-end testing technologies, and Google is also expanding its use of TSMC's advanced processes and CoWoS capacity.Intel is racing to advance its EMIB packaging platform, with major cloud companies like Meta and Google successively adopting the EMIB and EMIB-T platforms. ASE Technology Holding, positioned as a pure testing and packaging foundry, can directly procure organic embedded silicon bridge substrates to undertake backend wafer-level assembly and high-end testing services. Wu Tianyu, the Chief Operating Officer of ASE Technology Holding, believes that Intel's EMIB and TSMC's CoWoS are not zero-sum competitors. As the testing time for AI chips lengthens, the costs of equipment, materials, and labor are rising, and high-end packaging and testing capacity is becoming increasingly tight. Major testing and packaging factories have gradually raised prices based on products, capacity, and customer conditions, with increases of about 5% to 10%.
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