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first_img Analysis: China's storage is divided among CXMT, YMTC, and XMC

Researcher Schulz_Research stated that China's storage advancement is no longer a story of a single company, but rather a division of labor among three companies: CXMT is responsible for DRAM wafers, YMTC is responsible for NAND and has added DRAM in its latest factory, and the foundry controlled by YMTC, XMC, is responsible for stacking products from both. This division corresponds to the rules set by Beijing since late December last year, which state that new factory approvals must show that at least half of the equipment is domestically sourced, with exemptions only granted when there are no domestic options available. YMTC's Wuhan Phase III is the first advanced storage project to pass this rule and is set to begin production later this year.CXMT operates three 300mm DRAM factories, each producing about 100,000 wafers per month; models indicate it will reach 350,000 wafers by the end of 2026, and if all announced projects are completed, the total will exceed 600,000 wafers. YMTC's first two factories in Wuhan have a combined capacity of 200,000 wafers, with Phase III expected to reach 50,000 wafers by 2027 and full production of 100,000 wafers, along with plans to build two more factories of similar scale. XMC has two 12-inch factories, each with about 30,000 wafers, and an HBM packaging line producing about 3,000 wafers per month. China supplies about 10% of the global DRAM bits, with YMTC accounting for 14% of NAND bit shipments in the second quarter, and China consumes about 30% of global storage.CXMT has begun mass production of DDR5 and LPDDR5 and plans to start mass production of HBM3 this year, having already sent samples to domestic AI hardware developers. XMC has spent two years building HBM packaging based on hybrid bonding and YMTC's stacking IP, and is still advancing TSV technology.

Serenity: The storage prices and supply-demand structure remain tight, and a short-term increase does not indicate that the bottleneck has been broken

Serenity posted a reminder that the fundamentals of storage shortages have not changed and may even become more acute. The market will shift from one bottleneck sector to another, but the companies themselves remain unchanged; what changes are the valuations and narratives. Serenity added several pieces of evidence suggesting that the storage supply-demand gap may be worse than the market expects: Nikkei reported that Japanese distributors claim the storage demand gap has reached 40% to 60%, and prices may rise by about 50% by the end of the year; SpaceX has not accounted for the approximately $1.3 trillion capital expenditure from ultra-large cloud providers, and total spending may exceed expectations; SanDisk's expected gross margin of 80% is expected to be maintained until 2030; and order visibility for companies like Samsung has extended to 2031.Serenity emphasized that storage stocks are highly volatile, with some of its positions showing unrealized gains of over 270%, making them easier to hold. However, the company's operational fundamentals and short-term stock prices often do not align. The same logic applies to other bottleneck areas such as optical modules, CW lasers, and substrates; after a rebound in stock prices, there is no need to assume that shortages have ended. Storage prices and supply-demand structures remain tight, and market sentiment and valuation narratives are rapidly rotating.

first_img Micron warns that AI storage walls are intensifying, with HBM accounting for about 17% of the interruptions in Meta Llama 3 training

According to TrendForce, at Hot Chips 2026, Micron emphasized that the progress of AI computing power is faster than storage improvements, and the challenge of the "storage wall" is becoming increasingly prominent. Micron Fellow Raghu Sriramaneni pointed out that the computing power of AI accelerators increases approximately threefold every two years, while the bandwidth of HBM increases by less than double during the same period, and the gap may further widen. The deepening reliance on HBM also brings reliability issues; Micron cited Meta Llama 3 data indicating that HBM failures account for about 17% of unexpected training interruptions. New designs that blur the boundaries between computing and storage may help break through the bottleneck.The expansion of HBM also brings area and supply pressures: the latest generation of packaging integrates two GPUs with eight 12-layer HBM4 stacks, with storage accounting for about 90% of the semiconductor area, more than eight times the area occupied by GPUs; achieving equivalent capacity with HBM requires about three times the wafers of standard DDR5 DRAM. Thermal management has also become a key constraint, with solutions such as liquid cooling and ultra-thin chips being explored.Micron is advancing innovations in interconnect, packaging, and cooling, including SerDes and die-to-die PHY optimized for storage, larger size SiP and advanced packaging with glass substrates, as well as liquid cooling and hybrid bonding, and is developing fusion bonding to reduce thermal resistance and enhance data throughput.
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